1. Field of the Invention
The present invention relates to a ferroelectric memory device and a method of reading out data from the ferroelectric memory device.
2. Description of the Related Art
In recent years, attention has been paid to a ferroelectric memory device, as a semiconductor memory device, which has a ferroelectric capacitor wherein a ferroelectric material is used as a capacitor insulating film. As a ferroelectric memory device, there is known, for example, a memory which consists of series connected memory cells each having a transistor (T) having a source terminal and a drain terminal and a ferroelectric capacitor (C) in between said two terminals, hereafter named “series connected TC unit type ferroelectric RAM”. The series connected TC unit type ferroelectric RAM is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-255483, for instance. In the series connected TC unit type ferroelectric RAM, a plurality of unit cells share a plate line drive circuit. Thus, compared to conventional ferroelectric memory devices, the integration density of the memory cell array can be increased.
A data read-out method for a conventional series connected TC unit type ferroelectric RAM will now be briefly described with reference to FIG. 1. FIG. 1 is a timing chart of a word line WL potential, a block select signal BS, a plate line PL potential, a bit line pair BL & /BL potential.
In a standby state, all word lines WL are set at “H” level (cell transistors are turned on), and the block select signal BS is set at “L” level (a block select transistor is turned off). In addition, the plate line PL and the bit line pair BL & /BL are pre-charged at potential Vss (e.g. ground potential).
In a subsequent active state, the selected word line is set at “L” level and the block select signal BS is set at “H” level (time t1, t2). As a result, data is read out of the selected memory cell, and the potential of the bit line BL rises (t2 to t3). At the same time, the potential of bit line /BL rises by a reference potential Vref that is a reference for judging “0” data and “1” data. At time t3, a sense amplifier amplifies the data read out to the bit line BL. Specifically, if data is read out, and as a result, the potential of the bit line BL is lower than that of the bit line /BL, the read-out data is determined to be “0” data, and the bit line BL potential is amplified up to Vss. On the other hand, if the potential of the bit line BL is higher than that of the bit line /BL, the read-out data is determined to be “1” data and the bit line BL potential is amplified up to Vaa (e.g. internal power supply voltage).
Thereafter, the active state of the RAM is returned to the standby state, and the potentials of bit line pair BL & /BL are precharged at Vss.
In this manner, the data read-out is carried out in the series connected TC unit type ferroelectric RAM. However, the power consumption tends to increase in this prior-art data read-out method for the series connected TC unit type ferroelectric RAM. In particular, in the active state, the potential of the bit line /BL needs to be raised by the reference potential Vref, and the rise in power consumption due to this factor is conspicuous.